Intel Clearwater Forest Xeon CPUs will be making use of Foveros Direct technology to 3D Stack up to 288 cores on top of the base tile, says Bionic_Squash.
Intel Foveros Direct Technology To Be Utilized To 3D Stack Up To 288 Darkmont E-Cores Cores on Clearwater Forest Xeon CPUs
The Clearwater Forest CPUs are going to be the successor to the Sierra Forest Xeon chips which launch around mid-2024. These chips have one thing in common and that’s the use of E-Cores instead of P-Cores. The E-Cores used by Sierra Forest chips are codenamed Sierra Glen and are slightly modified versions of the Crestmont core architecture whereas the Darkmont cores used within Clearwater Forest chips are based on slightly modified versions of the Skymont cores.
Latest information suggests that Intel will be fully leveraging its hybrid bonding technology which is codenamed Foveros Direct for 3D Stacking of the Clearwater Forest Xeon CPUs. The CPU package is going to consist of a base tile on top of the interposer which is connected through a high-speed I/O, EMIB, and the cores will be sitting on the topmost layer.
For a quick recap of Intel’s Foveros Direct technology, it will allow direct copper-to-copper bonding, enabling low resistance interconnects and around 10-micron bump pitches. Intel itself states that Foveros Direct will blur the boundary between where the wafer ends and the package begins. The technology was previously disclosed to be manufacturing-ready by 2H 2023 however that has since changed.
It will be interesting to see the implementation of 3D Stacking (Foveros Direct) on the Intel Xeon E-Core family. Clearwater Forest chips are expected to feature up to 288 cores and 288 threads with significant improvements in IPC and efficiency. Another thing that was recently highlighted was the addition of higher cache on the package so it might be possible that the base tile itself incorporates extra pools of cache which will be directly connected to the cores sitting on the top layer. The Xeon Clearwater Forest CPUs are expected to launch in 2025 but we can expect more info from the blue team during its IFS direct keynote tomorrow.
Intel Xeon CPU Families (Preliminary):
| Family Branding | Diamond Rapids | Clearwater Forest | Granite Rapids | Sierra Forest | Emerald Rapids | Sapphire Rapids | Ice Lake-SP | Cooper Lake-SP | Cascade Lake-SP/AP | Skylake-SP |
|---|---|---|---|---|---|---|---|---|---|---|
| Process Node | Intel 20A? | Intel 18A | Intel 3 | Intel 3 | Intel 7 | Intel 7 | 10nm+ | 14nm++ | 14nm++ | 14nm+ |
| Platform Name | Intel Mountain Stream Intel Birch Stream |
Intel Mountain Stream Intel Birch Stream |
Intel Mountain Stream Intel Birch Stream |
Intel Mountain Stream Intel Birch Stream |
Intel Eagle Stream | Intel Eagle Stream | Intel Whitley | Intel Cedar Island | Intel Purley | Intel Purley |
| Core Architecture | Lion Cove? | Darkmont | Redwood Cove | Sierra Glen | Raptor Cove | Golden Cove | Sunny Cove | Cascade Lake | Cascade Lake | Skylake |
| MCP (Multi-Chip Package) SKUs | Yes | TBD | Yes | Yes | Yes | Yes | No | No | Yes | No |
| Socket | LGA 4677 / 7529 | LGA 4677 / 7529 | LGA 4677 / 7529 | LGA 4677 / 7529 | LGA 4677 | LGA 4677 | LGA 4189 | LGA 4189 | LGA 3647 | LGA 3647 |
| Max Core Count | Up To 144? | Up To 288 | Up To 136? | Up To 288 | Up To 64? | Up To 56 | Up To 40 | Up To 28 | Up To 28 | Up To 28 |
| Max Thread Count | Up To 288? | Up To 288 | Up To 272? | Up To 288 | Up To 128 | Up To 112 | Up To 80 | Up To 56 | Up To 56 | Up To 56 |
| Max L3 Cache | TBD | TBD | 480 MB L3 | 108 MB L3 | 320 MB L3 | 105 MB L3 | 60 MB L3 | 38.5 MB L3 | 38.5 MB L3 | 38.5 MB L3 |
| Memory Support | Up To 12-Channel DDR6-7200? | TBD | Up To 12-Channel DDR5-6400 | Up To 8-Channel DDR5-6400? | Up To 8-Channel DDR5-5600 | Up To 8-Channel DDR5-4800 | Up To 8-Channel DDR4-3200 | Up To 6-Channel DDR4-3200 | DDR4-2933 6-Channel | DDR4-2666 6-Channel |
| PCIe Gen Support | PCIe 6.0 (128 Lanes)? | TBD | PCIe 5.0 (136 Lanes) | PCIe 5.0 (TBD Lanes) | PCIe 5.0 (80 Lanes) | PCIe 5.0 (80 lanes) | PCIe 4.0 (64 Lanes) | PCIe 3.0 (48 Lanes) | PCIe 3.0 (48 Lanes) | PCIe 3.0 (48 Lanes) |
| TDP Range (PL1) | Up To 500W? | TBD | Up To 500W | Up To 350W | Up To 350W | Up To 350W | 105-270W | 150W-250W | 165W-205W | 140W-205W |
| 3D Xpoint Optane DIMM | Donahue Pass? | TBD | Donahue Pass | TBD | Crow Pass | Crow Pass | Barlow Pass | Barlow Pass | Apache Pass | N/A |
| Competition | AMD EPYC Venice | AMD EPYC Zen 5C | AMD EPYC Turin | AMD EPYC Bergamo | AMD EPYC Genoa ~5nm | AMD EPYC Genoa ~5nm | AMD EPYC Milan 7nm+ | AMD EPYC Rome 7nm | AMD EPYC Rome 7nm | AMD EPYC Naples 14nm |
| Launch | 2025? | 2025 | 2024 | 2024 | 2023 | 2022 | 2021 | 2020 | 2018 | 2017 |