Intel Lunar Lake CPU Mass Production Commences At TSMC Using N3B Node, First Laptops Heading For Q3 Launch

Intel’s Lunar Lake CPUs have entered the mass production stage at TSMC using their N3B node and the first laptops are expected in Q3 2024.

Intel’s Lunar Lake “Core Ultra 200V” CPUs Enter Mass Production At TSMC Using The Advanced N3B Process Node

Intel’s Lunar Lake CPUs are going to be Blue Team’s most advanced SOC to date, featuring lots of tiles on a single package along with on-package memory solutions in the form of LPDDR5x. These chips have now entered mass production at TSMC and will be utilizing the N3B process, making it the first Intel CPU to be entirely produced at TSMC.

Intel (Intel) will start the conversion of the new and old NB platforms in the second half of the year as scheduled. It will launch the Lunar Lake and Arrow Lake series at the end of the third quarter and fourth quarter respectively. The biggest highlight is the first release of Compute Tile from TSMC. Finally, it has used the 3nm customized process technology that TSMC has deployed for a long time, and has recently begun production

via DigiTimes

According to a report from DigiTimes, Intel has taken up the vast majority of orders of the TSMC 3nm process node, giving them the lead over competitors such as AMD, NVIDIA, and Qualcomm. Not only Lunar Lake “Core Ultra 200V” but the Arrow Lake “Core Ultra 200” CPUs will also utilize TSMC’s process technologies with the company anticipated to replace its own Intel 20A node for TSMC’s N3B node for certain tiles on Arrow Lake. The iGPU tile for Arrow Lake and Lunar Lake is also going to leverage TSMC process nodes.

Intel’s Arrow Lake and Lunar Lake CPUs are going to be very similar in terms of their compute tile which makes use of Lion Cove P-Cores and Skymont E-Cores. The main differences stem from the iGPU and I/O/SOC tiles which make use of different cores and technologies such as Alchemist & Alchemist+ Xe/Xe+ architectures for Arrow Lake CPUs and  Xe2 GPUs for Lunar Lake chips.

Intel’s Lunar Lake CPUs are expected to launch with the first laptops shipping in Q3 2024. These laptops will be Intel’s first Microsoft Copilot+ compliant devices however the Copilot+ features are going to be enabled through an update soon after launch and won’t ship with the laptops like is the case with Qualcomm’s Snapdragon X platform. Intel’s Arrow Lake CPUs will first target the desktop segment with reports of an October launch while the rest of the lineup for high-end & mainstream laptops will be shipping close to early 2025.

Intel Mobility CPU Lineup:

CPU Family Panther Lake Lunar Lake Arrow Lake Meteor Lake Raptor Lake Alder Lake
Process Node (CPU Tile) Intel 18A TSMC N3B Intel 20A
TSMC N3B
Intel 4 Intel 7 Intel 7
Process Node (GPU Tile) TSMC 3/2nm? TSMC N3B? TSMC N4? TSMC 5nm Intel 7 Intel 7
CPU Architecture Hybrid Hybrid Hybrid (Four-Core) Hybrid (Triple-Core) Hybrid (Dual-Core) Hybrid (Dual-Core)
P-Core Architecture Cougar Cove Lion Cove Lion Cove Redwood Cove Raptor Cove Golden Cove
E-Core Architecture Skymont? N/A Skymont Crestmont Gracemont Gracemont
LP E-Core Architecture (SOC) Skymont? Skymont Crestmont Crestmont N/A N/A
Top Configuration TBD 4+4 (MX Series) TBD 6+8 (H-Series) 6+8 (H-Series)
8+16 (HX-Series)
6+8 (H-Series)
8+8 (HX-Series)
Max Cores / Threads TBD 8/8? TBD 14/20 14/20 14/20
Planned Lineup H/P/U Series V-Series H/P/U Series H/P/U Series H/P/U Series H/P/U Series
GPU Architecture Xe3-LPG (Celestial) Xe2-LPG (Battlemage) Xe-LPG (Alchemist) Xe-LPG (Alchemist) Iris Xe (Gen 12) Iris Xe (Gen 12)
GPU Execution Units TBD 64 EUs 192 EUs 128 EUs (1024 Cores) 96 EUs (768 Cores) 96 EUs (768 Cores)
Memory Support TBD LPDDR5X-8533 TBD DDR5-5600
LPDDR5-7400
LPDDR5X – 7400+
DDR5-5200
LPDDR5-5200
LPDDR5-6400
DDR5-4800
LPDDR5-5200
LPDDR5X-4267
Memory Capacity (Max) TBD 32 GB TBD 96 GB 64 GB 64 GB
Thunderbolt Ports TBD TBD TBD 4 (TB4) 4 (TB4) 4 (TB4)
WiFi Capability TBD WiFi 7 TBD WiFi 6E WiFi 6E WiFi 6E
TDP TBD 17-30W TBD 7W-45W 15-55W 15-55W
Launch 2H 2025 2H 2024 2H 2024 2H 2023 1H 2023 1H 2022

News Source: Dan Nystedt

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